Design and Implementation of an Adaptive Execution Unit (AEU): A Low-Power Modular Architecture with Complete RTL-to-GDSII Implementation

Abstract

The Arithmetic Logic Unit (ALU) is a fundamental component of modern processors, responsible for arithmetic, logical, comparison, and shift operations. Conventional ALU architectures face rising power consumption, limited scalability, and inefficient hardware utilization, and most existing designs stop at RTL functionality without addressing complete ASIC implementation. This work presents the design and implementation of an Adaptive Execution Unit (AEU), a modular execution architecture that integrates dedicated arithmetic, logical, multiplier, divider, comparator, and barrel-shifter modules under a centralized control unit. A dynamic precision controller activates only the datapath slices required by an operation, while integrated clock gating and operand isolation reduce unnecessary switching activity. The design is described in synthesizable Verilog HDL and implemented through an industrial RTL-to-GDSII flow using Cadence Genus for synthesis and Cadence Innovus for physical design, covering floorplanning, placement, clock-tree synthesis, routing, timing analysis, and physical verification. Results confirm positive timing slack, 97.5% clock-gated flip-flops, 0% routing congestion, and full antenna and DRC/LVS compliance, demonstrating an efficient, scalable, and implementation-aware execution architecture suitable for modern VLSI processors.