Felix Academic Publications International Journal of Innovative Trends in Engineering Science and Technology 3139-6887 1 5 2026 10 06 Typical mode Serial Peripheral Interface (SPI) master controller based on APB with clock optimization 8 11 10.5281/zenodo.22131568 eng VIKRAM KEERTHANA JNTUGV Miracle Educational Society Group of Institutions P SRIDEVI JNTUGV Miracle Educational Society Group of Institutions D RAJITHA JNTUGV Miracle Educational Society Group of Institutions IJITEST-2026-019 10.5281/zenodo.22131568 2026 07 03 2026 07 27 A configurable SPI interface based on APB bus using four slaves is proposed in this thesis. The SPI interface transmission information is configured through APB bus, which can realize the master-slave mode switching, 4 kinds of clock transmission mode switching and MSB/LSB communication mode switching. Meanwhile the transmission rate can be selected and the transmission length can be variable from 1 to 32 bits. Based on the SPI transmission protocol, the proposed design uses a finite state machine method to control the transmission timing of the SPI interface. This design was verified through RTL simulation and Verilog testbench for verification. The verification results show that the functional of SPI interface is correct and the data transmission is stable.