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<ArticleSet>
  <Article>
    <Journal>
      <PublisherName>Felix Academic Publications</PublisherName>
      <JournalTitle>International Journal of Innovative Trends in Engineering Science and Technology</JournalTitle>
      <Issn>3139-6887</Issn>
      <Volume>1</Volume>
      <Issue>4</Issue>
      <PubDate PubStatus="epublish">
        <Year>2026</Year>
        <Month>08</Month>
        <Day>01</Day>
      </PubDate>
    </Journal>
    <ArticleTitle>Configurable Cyclic Redundancy Check generator and checker with error detection coverage analysis for PCIe application </ArticleTitle>
    <FirstPage>4</FirstPage>
    <LastPage>7</LastPage>
    <ELocationID EIdType="doi">10.5281/zenodo.22847850</ELocationID>
    <Language>eng</Language>
    <AuthorList>
      <Author>
        <FirstName>MADUGULA</FirstName>
        <LastName>POORNIMA</LastName>
        <AffiliationInfo>
          <Affiliation>JNTUGV Miracle Educational Society Group of Institutions</Affiliation>
        </AffiliationInfo>
      </Author>
      <Author>
        <FirstName>Mrs. D</FirstName>
        <LastName>RAJITHA</LastName>
        <AffiliationInfo>
          <Affiliation>JNTUGV Miracle Educational Society Group of Institutions</Affiliation>
        </AffiliationInfo>
      </Author>
      <Author>
        <FirstName>Mrs. P</FirstName>
        <LastName>SAILAJA</LastName>
        <AffiliationInfo>
          <Affiliation>JNTUGV Miracle Educational Society Group of Institutions</Affiliation>
        </AffiliationInfo>
      </Author>
    </AuthorList>
    <ArticleIdList>
      <ArticleId IdType="pii">IJITEST-2026-016</ArticleId>
      <ArticleId IdType="doi">10.5281/zenodo.22847850</ArticleId>
    </ArticleIdList>
    <History>
      <PubDate PubStatus="received">
        <Year>2026</Year>
        <Month>07</Month>
        <Day>27</Day>
      </PubDate>
      <PubDate PubStatus="accepted">
        <Year>2026</Year>
        <Month>08</Month>
        <Day>01</Day>
      </PubDate>
    </History>
    <Abstract>In this thesis CRC is applied for PCIe(Pheripheral Component Interconnect Express ) transmission in Data Link Layer .Link CRC is implemented and verified using Verilog.In an advanced transmission system, an error occurred when a bit  adjusts in the middle of transmission and gathering in a channel. A binary 1 is moved and a binary 0 is getting  or a binary 0 is moved and a binary 1 is getting. 
Cyclic Redundancy  Check is the most important method to detect the errors occurred during transmission of any data. Errors transpired in communication due to internal and external factors i.e. due to components, link, design, noise and interference etc. This work is focused on study of encoder and decoder of CRC</Abstract>
    <ObjectList>
      <Object Type="keyword">
        <Param Name="value">PCIe</Param>
      </Object>
      <Object Type="keyword">
        <Param Name="value">Data link layer</Param>
      </Object>
      <Object Type="keyword">
        <Param Name="value">Lcrc</Param>
      </Object>
      <Object Type="keyword">
        <Param Name="value">crc generator and checker.</Param>
      </Object>
    </ObjectList>
  </Article>
</ArticleSet>