IJITEST International Journal of Innovative Trends in Engineering Science and Technology IJITEST 3139-6887 Felix Academic Publications IJITEST-2026-019 10.5281/zenodo.22131568 Original Research Articles Research Article Typical mode Serial Peripheral Interface (SPI) master controller based on APB with clock optimization KEERTHANA VIKRAM keerthanavikram5@gmail.com SRIDEVI P dpakki@miracleeducationalsociety.com RAJITHA D rdatla@miracleeducationalsociety.com JNTUGV Miracle Educational Society Group of Institutions 06 10 2026 1 5 8 11 03 07 2026 27 07 2026 Copyright © 2026 VIKRAM KEERTHANA, P SRIDEVI, D RAJITHA. Published by Felix Academic Publications. 2026 VIKRAM KEERTHANA, P SRIDEVI, D RAJITHA This is an open-access article distributed under the terms of the Creative Commons Attribution 4.0 International (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are properly credited.

A configurable SPI interface based on APB bus using four slaves is proposed in this thesis. The SPI interface transmission information is configured through APB bus, which can realize the master-slave mode switching, 4 kinds of clock transmission mode switching and MSB/LSB communication mode switching. Meanwhile the transmission rate can be selected and the transmission length can be variable from 1 to 32 bits. Based on the SPI transmission protocol, the proposed design uses a finite state machine method to control the transmission timing of the SPI interface. This design was verified through RTL simulation and Verilog testbench for verification. The verification results show that the functional of SPI interface is correct and the data transmission is stable.

 SPI Interface APB bus clock polarity clock phase. Article Overview

A configurable SPI interface based on APB bus using four slaves is proposed in this thesis. The SPI interface transmission information is configured through APB bus, which can realize the master-slave mode switching, 4 kinds of clock transmission mode switching and MSB/LSB communication mode switching. Meanwhile the transmission rate can be selected and the transmission length can be variable from 1 to 32 bits. Based on the SPI transmission protocol, the proposed design uses a finite state machine method to control the transmission timing of the SPI interface. This design was verified through RTL simulation and Verilog testbench for verification. The verification results show that the functional of SPI interface is correct and the data transmission is stable.