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    <journal-meta>
      <journal-id journal-id-type="publisher-id">IJITEST</journal-id>
      <journal-title-group>
        <journal-title>International Journal of Innovative Trends in Engineering Science and Technology</journal-title>
        <abbrev-journal-title abbrev-type="publisher">IJITEST</abbrev-journal-title>
      </journal-title-group>
      <issn pub-type="epub">3139-6887</issn>
      <publisher>
        <publisher-name>Felix Academic Publications</publisher-name>
      </publisher>
      <self-uri xlink:href="https://ijitest.org"/>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="publisher-id">IJITEST-2026-016</article-id>
      <article-id pub-id-type="doi">10.5281/zenodo.22847850</article-id>
      <article-categories>
        <subj-group subj-group-type="heading">
          <subject>Original Research Articles</subject>
        </subj-group>
        <subj-group subj-group-type="article-type">
          <subject>Research Article</subject>
        </subj-group>
      </article-categories>
      <title-group>
        <article-title>Configurable Cyclic Redundancy Check generator and checker with error detection coverage analysis for PCIe application </article-title>
      </title-group>
      <contrib-group>
      <contrib contrib-type="author" corresp="yes">
        <name>
          <surname>POORNIMA</surname>
          <given-names>MADUGULA</given-names>
        </name>
        <email>poornimamadugula@gmail.com</email>
        <xref ref-type="aff" rid="aff1"/>
      </contrib>
      <contrib contrib-type="author">
        <name>
          <surname>RAJITHA</surname>
          <given-names>Mrs. D</given-names>
        </name>
        <email>rdatla@miracleeducationalsociety.com</email>
        <xref ref-type="aff" rid="aff1"/>
      </contrib>
      <contrib contrib-type="author">
        <name>
          <surname>SAILAJA</surname>
          <given-names>Mrs. P</given-names>
        </name>
        <email>spededa@miracleeducationalsociety.com</email>
        <xref ref-type="aff" rid="aff1"/>
      </contrib>
      </contrib-group>
    <aff id="aff1">
      <institution-wrap>
        <institution content-type="orgname">JNTUGV Miracle Educational Society Group of Institutions</institution>
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      <pub-date date-type="pub" publication-format="electronic">
        <day>01</day>
        <month>08</month>
        <year>2026</year>
      </pub-date>
      <volume>1</volume>
      <issue>4</issue>
      <fpage>4</fpage>
      <lpage>7</lpage>
      <history>
        <date date-type="received" iso-8601-date="2026-07-27">
          <day>27</day>
          <month>07</month>
          <year>2026</year>
        </date>
        <date date-type="accepted" iso-8601-date="2026-08-01">
          <day>01</day>
          <month>08</month>
          <year>2026</year>
        </date>
      </history>
      <permissions>
        <copyright-statement>Copyright &#169; 2026 MADUGULA POORNIMA, Mrs. D RAJITHA, Mrs. P SAILAJA. Published by Felix Academic Publications.</copyright-statement>
        <copyright-year>2026</copyright-year>
        <copyright-holder>MADUGULA POORNIMA, Mrs. D RAJITHA, Mrs. P SAILAJA</copyright-holder>
        <license xlink:href="https://creativecommons.org/licenses/by/4.0/">
          <license-p>This is an open-access article distributed under the terms of the Creative Commons Attribution 4.0 International License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are properly credited.</license-p>
        </license>
      </permissions>
      <self-uri content-type="html" xlink:href="https://ijitest.org/archives/volume1/issue4/IJITEST-2026-016"/>
      <self-uri content-type="pdf" xlink:href="https://ijitest.org/api/files/published/IJITEST-2026-016-published.pdf"/>
      <abstract xml:lang="en">
        <p>In this thesis CRC is applied for PCIe(Pheripheral Component Interconnect Express ) transmission in Data Link Layer .Link CRC is implemented and verified using Verilog.In an advanced transmission system, an error occurred when a bit  adjusts in the middle of transmission and gathering in a channel. A binary 1 is moved and a binary 0 is getting  or a binary 0 is moved and a binary 1 is getting. 
Cyclic Redundancy  Check is the most important method to detect the errors occurred during transmission of any data. Errors transpired in communication due to internal and external factors i.e. due to components, link, design, noise and interference etc. This work is focused on study of encoder and decoder of CRC</p>
      </abstract>
      <kwd-group kwd-group-type="author-keywords">
        <kwd>PCIe</kwd>
        <kwd>Data link layer</kwd>
        <kwd>Lcrc</kwd>
        <kwd>crc generator and checker.</kwd>
      </kwd-group>
    </article-meta>
  </front>
  <body>
    <sec id="sec-summary">
      <title>Article Overview</title>
      <p>In this thesis CRC is applied for PCIe(Pheripheral Component Interconnect Express ) transmission in Data Link Layer .Link CRC is implemented and verified using Verilog.In an advanced transmission system, an error occurred when a bit  adjusts in the middle of transmission and gathering in a channel. A binary 1 is moved and a binary 0 is getting  or a binary 0 is moved and a binary 1 is getting. 
Cyclic Redundancy  Check is the most important method to detect the errors occurred during transmission of any data. Errors transpired in communication due to internal and external factors i.e. due to components, link, design, noise and interference etc. This work is focused on study of encoder and decoder of CRC</p>
    </sec>
  </body>
  <back>
    <sec sec-type="declarations">
      <title>Declarations</title>
      <p>The authors declare that no competing interests exist in relation to this published work.</p>
    </sec>
  </back>
</article>