IJITEST_20261027163123_IJITEST-2026-018 20261027163123 International Journal of Innovative Trends in Engineering Science and Technology editor@ijitest.org Felix Academic Publications International Journal of Innovative Trends in Engineering Science and Technology IJITEST 3139-6887 07 2026 1 5 Mr. PARADI RAMESH JNTUGV Miracle Educational Society Group of Institutions Dr. A VENKATESWARA RAO JNTUGV Miracle Educational Society Group of Institutions Mr. CH SUBBARAO JNTUGV Miracle Educational Society Group of Institutions The FSM design for I2C master recovery mechanism is proposed in this thesis, this recovery mechanism has different staes. The I2C or Inter-Integrated Circuit protocol is a serial communication protocol . I2C is a bidirectional 2-wire bus designed to enhance hardware efficiency and increase simplicity of the circuit. This protocol bolsters multiple masters (which is a limitation with SPI communication) and multiple slaves and also allows communication between faster and slower devices by a serial data bus (SDA) without data loss. The other line is Serial clock line (SCL) which transfers the data according to a synchronized clock which is a limitation for UART communication. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. Other types of communication protocols like USB, RS-422, RS-485, CAN etc. require more pin connections and signals for communication. The postulatesof I2C over UART, SPI, USB and other protocols indicates I2C’s significance in its use as communication protocol. This thesis makes use of Verilog language in designing and Implementing I2C bus on EDA playground(Aldec Riviera 2025.05 ) ,verified and simulated the FSM for I2C protocol recover mechanism. 07 30 2026 5 7 https://creativecommons.org/licenses/by/4.0/ 10.5281/zenodo.22847710 https://ijitest.org/article/ijitest-2026-018 https://ijitest.org/api/files/published/IJITEST-2026-018-published.pdf https://ijitest.org/api/files/published/IJITEST-2026-018-published.pdf