IJITEST_20260930184412_IJITEST-2026-016 20260930184412 International Journal of Innovative Trends in Engineering Science and Technology editor@ijitest.org Felix Academic Publications International Journal of Innovative Trends in Engineering Science and Technology IJITEST 3139-6887 09 2026 1 4 MADUGULA POORNIMA JNTUGV Miracle Educational Society Group of Institutions Mrs. D RAJITHA JNTUGV Miracle Educational Society Group of Institutions Mrs. P SAILAJA JNTUGV Miracle Educational Society Group of Institutions In this thesis CRC is applied for PCIe(Pheripheral Component Interconnect Express ) transmission in Data Link Layer .Link CRC is implemented and verified using Verilog.In an advanced transmission system, an error occurred when a bit adjusts in the middle of transmission and gathering in a channel. A binary 1 is moved and a binary 0 is getting or a binary 0 is moved and a binary 1 is getting. Cyclic Redundancy Check is the most important method to detect the errors occurred during transmission of any data. Errors transpired in communication due to internal and external factors i.e. due to components, link, design, noise and interference etc. This work is focused on study of encoder and decoder of CRC 08 01 2026 4 7 https://creativecommons.org/licenses/by/4.0/ 10.5281/zenodo.22847850 https://ijitest.org/article/ijitest-2026-016 https://ijitest.org/api/files/published/IJITEST-2026-016-published.pdf